Sasan H. Ardalan and Tulay Adali XCAD Corp., 659 Cary Towne Blvd, Suite 106, Cary, NC 27511 Department of Electrical Engineering, University of Maryland Baltimore County
Graphical block diagram simulation tools with highly interactive plotting and visualization capabilities can accelerate and greatly improve the educational process in DSP and Communication courses. In this paper, we describe three ways we have used the graphical simulation tool Capsim in DSP and Communication courses: in an advanced graduate course, a senior undergraduate course in parallel with lab experiments, and for simulation of DSP algorithms implemented on Digital Signal Processors in mixed analog and digital domains. We discuss our experiences in these courses, and the importance of true multi-rate signal processing capability for studying advanced topics in DSP. As an example, we discuss the importance of a synchronous data flow block diagram simulation in the design and simulation of both the network and physical layer in communications systems. We highlight the insights that students gain about error free transmission over noisy channels by using these tools.
In this paper we will describe simulation projects based on Capsim which were used in both senior undergraduate and advanced graduate courses at North Carolina State University and at University of Maryland Baltimore County.
In an advanced graduate level course at North Carolina State University the following topics were covered: timing recovery, delta-sigma modulation, and baseband digital communication with adaptive feedback equalization in the presence of multipath fading channels. In the timing recovery project, a binary data stream is generated at the given bit rate, encoded, oversampled, pulse-shaped and transmitted over an analog channel. At the receiver, the recovered clock with jitter (modeled at a high sampling rate) resamples the filtered signal producing baseband samples at a lower rate. A sample Capsim topology for this project is shown in Figure 1. In the delta sigma modulation project, the oversampled bit stream is decimated and filtered requiring two stage sampling rate conversion.
These projects represent a sampling of cases in which multi-rate signal processing is necessary both in implementation and in modeling. In fact, multi-rate signal processing should be the essential component in a DSP and communications course.
With simulation tools such as Capsim, the students can visualize the effects of multi-rate signal processing in the time and frequency domains, and thus connect simulations with the real world of mixed analog and digital signal processing systems. Also, by supporting true multi-rate signal processing, where blocks process samples at the true rate, we can achieve a greater match between
simulation and practice which all make multi-rate signal processing an essential part of DSP and communications education. To simulate true multi-rate signal processing the block diagram simulation tool must use an appropriate buffering scheme to connect blocks. The random access buffers employed in Capsim which are based on the implementation described in \cite{messer} achieve this goal.
Block diagram simulation tools based on the asynchronous data flow paradigm offer greater modeling flexibility beyond true multi-rate capability. We will describe the combined network and physical layer simulation of error free transmission over a noisy channel in this paper. The purpose of this example is to illustrate the benifits of ADF simulators in solving challanging communications problems that are encountered in present and future systems. It is imperative that students and engineers be equiped with such tools. The ability to simulate at the network level while maintaining accurate and detailed simulation of the physical layer provides the foundation for accellerated learning of complex problems, the ability to exercise protocols over realistic channels, and rapid prototyping of new protocols for existing and new data pumps and channel environments.
Block diagram simulation tools which are based on the asynchronous data flow paradigm include and are not limited to (1),(2), (3).
In the senior communication course, Capsim simulations are done in parallel with the laboratory experiments, and are used for verification of the lab test results. The main lab project is the design of a multiplexed PCM system using the Intel 2916 single chip combo CODEC.
The Capsim topology for the voiceband Codec experiment is shown in Figure 1. The top level block diagram consists of a sine wave generator, a transmitter, a receiver, a signal to total distortion measurement block, probes, and an X-Y display. The transmitter galaxy,TxCodec, first filters the input signal to eliminate 60 Hz. interference, and also band-limits the signal to prevent aliasing. The filtered signal is sampled by a sample and hold block with sampling rate set at 64kHz which is 8 times the sampling rate of the codec. The sampled signal then goes through an A/D and a mu-law compressor, compressing 13 bits to 8 bits. At the receiver galaxy, RxCodec, the 8 bit samples are mapped to 13 bit uniform samples by the mu-law expander which are then converted to analog and then lowpass filtered to reproduce the transmitted waveform. By inserting probes with various postprocessing functions to connections at any level in the topology and by changing the functionality of the blocks by varying their parameters, we can investigate the behavior of the Codec under a variety of conditions. For example in Figure 2, we have a group plot for comparison of received signal spectrum for various levels, an X-Y plot of input signal versus output signal for phase measurement, and the analog waveform at the receiver digital to analog converter output. As seen in this example, the simulator easily models an inherently analog system through over-sampling.
An important aspect of supplementing the lab with Capsim simulations is that the CODEC chip combines the filtering and A/D and D/A on a single chip. Thus students do not have access to signals inside the chip. With block diagram simulation, however, they can examine signals prior to and after sampling and filtering. In the lab, students must describe the output spectrum in terms of the linear and nonlinear processing that the signal has undergone in order to describe the features of the spectrum. This is done with various frequencies and levels. All phenomenom such as nonlinear quantization, aliasing, and filtering can be obserevd in the output spectrum. Block diagram simulation allows the students to experiment with signals internal to the CODEC.
The availability of interactive graphical block diagram simulation tools has resulted in accelerated learning of advanced digital communication topics in graduate courses. Moreover, students have gained greater insight into subjects by designing and simulating systems and verifying theory. Previously, students were limited to text book problems and one or two computer projects, if any, in which a great amount of time was expended in issues unrelated to the subjects. In an advanced graduate course in digital communications, students were asked to verify the theoretical concepts in journal papers by simulations, such as joint carrier phase and symbol timing recovery following the theory developed in (4). A number of projects based on Capsim were given during the semester to enhance the students grasp of theory.
The course included one independent project in which students were given open ended problem to stimulate creativity and to encourage them to explore concepts more thoroughly. The probect involved the design of a digital communication system with timing recovery, adaptive fractionaly spaced equalization with decision feedback and a fading channel model. Obviously, if the students had to rely on writing programs or using cumbersome plotting routines, we could not have covered this material. Furthermore, students would have been discouraged from experimentation and exploration of new topics and ideas.
Since writting custom models and integrating them into Capsim is very simple, students could develop their own blocks instead of relying on library blocks.
An example system used in the course is shown in Figure 1.
In practice, a digital communication system involves multiple sampling rates. It is emperative that the simulation tools support true multi-rate sampling. That is, each block processes samples at its true rate and is not oversampled. This statement is based on the fact that block diagram simulation tools must help students break away from the simple implementation of analog systems in the digital domain. Students must be able to easily work with algorithms that take advantage of digital signal processing devorced of rollover techniques from the analog domain. This requires hands on experience with multi-rate sampling and a greater grasp of sampling rates and the connection between simulation and practice.
Capsim allows blocks to process samples at their true rate. A binary source produces binary data at the bit rate with no oversampling required, although an analog channel is being modeled. In a typical digital communication link, the bits are coded into an in phase and quadrature channel. In this case, the sampling rate for each channel may be reduced by a factor of four for example. The in phase and quadrature phase samples are then increased in sampling rate for pulse shaping. In figure 2, we show a system for simulating a v.29 modem . The lower block diagram shows the transmitter topology. The figure shows the received constellation and eye diagram of the in-phase channel. The transmitter topology has three probes. These probes collect samples and display them in a multi-channel plot shown in Figure ?. This figure clearly shows the multi-rate sampling involved in the transmitter. The lower channel shows the bit stream produced at the bit rate. There are 256 bits generated. The middle channel shows the in phase symbols. Every 4 bits maps to one in-phase sample so the rate is one fourth of the bit rate and there are 64 in-phase samples. The in-phase samples are then up-sampled by 16 and filtered by the square root Nyquist filter. The resulting waveform is shown in the top channel.
A direct consequence of the ADF paradigm in block diagram simulators is the speed of these simulators compared to other simulators. This is clearly illustrated in the example above since each block process exactly the number of samples at its natural rate. In other simulation systems, all blocks process at the highest sampling rate. This forces the student to adjust to a limitation in the simulator and not to the problem at hand.
The above has a direct impact on the generation of C- code for implementation on programmable DSP's. Obviously, the ADF simulation system will theoretically produce more efficient code. However, the overhead associated with buffer management is still an issue that requires further research(5). However, this is important work since a major goal of introducing students to high level block diagram simulation tools is to expose them to the concepts of hardware synthesis from high level block diagram designs.
To prepare students for the complexities and chalanges involved in error free transmission over wire and mobile channels, the simulation tool must be capable of both accurate physical layer simulation and network level simulation.
Capsim combines both network level and physical layer simulation models due to the great flexibility offered by random access buffers, custom buffer design, and the ADF paradigm.
Figure 3, shows a Capsim simulation of error free transmission with a v.29 CODEC in a noisy channel. For a detailed discussion of the problem and the simulation system see (6). Here we present a brief overview of the simulation system. The digital data from the binary data generator are encoded into HDLC frames and transmitted to the CCITT v.29 MODEM. The decoded received bits are inputted to the receiver where the HDLC frames are examined for errors. If an error is detected, the receiver sends a reject acknowledgment (NAK) along with the frame number it expects to receive next ( modulo 8) to the transmitter. If a correct frame is received a positive acknowledgment is sent to the tranmitter(ACK). The positive acknowledgements from the receiver are sent through the "rts" block to the data generator. The data generator will output a block of data ( the payload bits) only if an ACK has been received. The transmitter "txhdlc" maintains a queue which it uses to retransmit frames that were corrupted by the physical layer and received in error. The connections which contain the receiver acknowledgements are shown with dashed lines. This system involves asynchronous operation were various buffers transfer a random number of bits during the transmission of a frame. This is due to the HDLC protocol in which bit stuffing is used. Also, the HDLC frame contains an 8 bit address, 8 bit control field, the payload, a 16 bit frame check sequence, and beginning and ending flags. Due to retransmissions, the number of receiver acknowlegments is also random. The v.29 CODEC at the physical layer involves multiple sampling rates.
In the simulation in Figure 3 (same one), 4096 bits are transmitted with a payload of 64 bits or 64 frames total (4096/64). The simulation results in Figure ? (same one) show a plot of the received constellation showing the noisy channel. The bit error rate was 0.01315. Note that 133 frames were transmitted over the v.29 codec. Of these 56 were retransmissions due to errors in the received frame. Altogether, 16014 bits were transmitted out.
Of interest is the plot of the receiver acknowledgements. When the acknowledgement value exceeds 140, we have an NAK. The ramp shows the number of the expected frame number. The Request-To-Send plot shows the ACK's from the receiver. There are 64 ACK's with the frame number modulo 8 indicated by the ramps.
The plot of the receiver acknowledgements shows the retransmission of erroneous frames. In many cases more than 4 retransmissions were required.
It is obvious that with the combined network and physical layer simulation in Capsim students can easily understand the dynamics and random nature of error free transmission in noisy channels. They can experiment with various parameters and examine their effect on throughput. We can better equip students with the necessary tools and knowledge to tackle real-world problems with an understanding of two very different domains.
We can also simulate DSP algorithms implemented on digital signal processors in mixed analog and digital domains in the Capsim environment. In order to debug and develop algorithms on DSP's, the digital signal processor must be simulated in a complete system. This is accomplished by implementing the full functionality of the DSP in a single block. The input and output buffers to the block are directly related to the input/output ports of the DSP. Using probes and signal generators, filters and channels, problems and bugs can be identified by viewing plots of waveforms rather than browsing through files produced by conventional DSP simulators. The speed at which a DSP can be excited and results observed in the Capsim environment has lead to rapid development and debugging of algorithms. After simulation in the Capsim environment, the DSP code is downloaded to an emulator or DSP card. This technique saves many frustrating hours of debugging in hardware or by producing input and output files in computer based DSP simulators. The key is to expose students to rapid prototyping and testing of designs using the power of interactive graphical block diagram simulation tools. Obviously, students who have mastered these techniques have a definite edge in designing and rapidly introducing new designs into projects. Figure ? shows a Capsim simulation in which a block simulates a TMS320C25 which implements a lowpass filter. The filter code is an object file which is specified by the blocks parameter. Many TMS320C25 blocks can be simulated where each block implements a specific algorithm or implments a full system such as a modem.
1- Messerschmitt D., ``Structured Interconnection of Simulation Programs,''
in Proc. IEEE Globecom, 1984.
2- J. Kunkel, "COSSAP: A Stream driven simulator,", presented at IEEE Int. Workshop Microelectrion. Commun., Interlaken, Switzerland, March 1991}
3- Capsim { XCAD Corp., Cary, NC }.
4- Ali Sadri, Masters Thesis, North Carolina State University, May 1991
5- Sebastian Ritz, Matthias Pankert, Vojin Zivojnovic, and
Heinrich Meyr," High-Level Software Synthesis for the Design of
Communication Systems", IEEE Journal on Selected Areas in Communications,
Vol. II, No. 3, April 1993
7- Lee, A.E., ``A Design Lab for Statistical Signal Processing,''
in Proc. IEEE Int. Conf. Acoust.,
Speech, Signal Processing (San Francisco, CA), March 1992, vol 4, pp. 81-84.
8- Chassaing R., Anakwa W., and Richardson A., `` Real-time signal processing
in education,'' in Proc. IEEE Int. Conf. Acoust.,
Speech, Signal Processing (Minneapolis, MN), April 1993, vol 1, pp. 28-31.
9- Adali, T. and Ardalan, S. H., ``A mobile communications
application in block diagram simulator Capsim,''
in Simulators , Simulation Series, vol. 25, no. 4,
pp. 535-540, March 1993.
5- Meyers, M.H. and Franks, L.E., ``Joint carrier phase and symbol timing recovery for PAM systems,'' in IEEE Trans. on Comm., vol. com-28, no.8, Aug 1980,
pp. 1121-1136.